Semiconductor storage device

ABSTRACT

In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided. The semiconductor storage device includes a phase change thin film  101  having two stable phases of a crystal state with low electric resistance and an amorphous state with high electric resistance, upper plug electrodes  102  and  103  provided on one side of the phase change thin film  101 , a lower electrode  104  provided on the other side of the phase change thin film  101 , a selecting transistor  114  whose drain/source terminals are connected to the upper plug electrode  102  and the lower electrode  104 , and a selecting transistor  115  whose drain/source terminals are connected to the upper plug electrode  103  and the lower electrode  104 , and a first memory cell is configured with the selecting transistor  114  and a phase change region  111  in the phase change thin film  101  sandwiched between the upper plug electrode  102  and the lower electrode  104 , and a second memory cell is configured with the selecting transistor  115  and a phase change region  112  in the phase change thin film  101  sandwiched between the upper plug electrode  103  and the lower electrode  104.

TECHNICAL FIELD

The present invention relates to a semiconductor storage device, andmore particularly, the present invention relates to a techniqueeffectively applied to a semiconductor integrated circuit device having:a high density integrated memory circuit including a memory cell using aphase change material particularly represented by a chalcogenidematerial; a logic mixedly mounted memory in which a memory circuit and alogic circuit are provided on the same semiconductor substrate; or ananalog circuit. Particularly, the present invention relates to astructure in which memory cells are arranged in high density so that ahigh-speed drive can be achieved.

BACKGROUND ART

A semiconductor nonvolatile memory is frequently used for mobileequipment such as a mobile phone, and in recent years, a market thereofhas been increasingly spread. Currently, the semiconductor nonvolatilememory which is most utilized is a FLASH memory. However, since arewriting speed thereof is essentially slow, it is mainly used as aprogrammable ROM, an information storage device for a still camera, inwhich the rewriting is not frequently performed, or the like. Also,since the FLASH memory requires large power consumption at the rewritingtime, it includes a large issue from the viewpoint of reduction ofbattery exhaustion which is important for mobile terminal equipment.

On the other hand, since a high-speed RAM is required as a workingmemory, both memories of the FLASH memory and a DRAM are mixedly mountedin the mobile terminal equipment. If a device provided withcharacteristics of these two memories can be realized, an impact of thedevice is extremely large in that it becomes possible not only tointegrate the FLASH memory and the DRAM on one chip but also to replaceall semiconductor memories with the device.

As one of candidates for realizing the device which has low powerconsumption and high rewriting speed and is suitable also for theworking memory of the mobile terminal equipment, there is a nonvolatilememory using a phase change film.

As already known, materials capable of switching reversibly from onephase to the other phase are used for the phase change memory. A readingis possible by a difference between electric characteristics of thesephase states. For example, these materials can change between adisordered phase of an amorphous state and an ordered phase of a crystalstate. The amorphous state has an electric resistance higher than thatof the crystal state, so that information can be stored by using thedifference between the electric resistances.

The material suitable for the phase change memory cell is an alloycontaining at least one element of sulfur, selenium, and tellurium, suchan alloy being called “chalcogenide”. Currently, a most comingchalcogenide is an alloy made of germanium, antimony, and tellurium(Ge₂Sb₂Te₅), and the alloy has been already widely used for informationstorage media of a rewritable optical disk.

In the phase change memory, information storage is performed by using adifference between phase states of the chalcogenide. A phase change fromthe crystal state to the amorphous state or a reverse phase change fromthe amorphous state to the crystal state can be obtained by locallyraising temperature of the chalcogenide. Although depending on the phasechange material, its composition, and the like, both phases aregenerally stabilized at approximately 130° C. or lower so thatinformation is stably retained. Also, when the chalcogenide is held at acrystallization temperature of 200° C. or higher for a sufficientperiod, the phase thereof changes to the crystal state. Acrystallization time changes depending on the composition of thechalcogenide and the holding temperature. In a case of Ge₂Sb₂Te₅, thecrystallization time thereof is, for example, 150 nanoseconds. Forreturning the chalcogenide to the amorphous state, the temperature israised to a melting point thereof (approximately 600° C.) or higher andrapidly lowered to cool.

As a method of raising the temperature, a current is carried to thechalcogenide to heat by Joule heat generated from an inside of thechalcogenide or an electrode adjacent thereto. Hereinafter, thecrystallization of the chalcogenide of the phase change memory cell iscalled a “set operation”, and the amorphization thereof is called a“reset operation”. Also, a state in which a phase change portion hasbeen crystallized is called a “set state”, and a state in which thephase change portion has been amorphized is called a “reset state”. Aset time is, for example, 150 nanoseconds, and a reset time is, forexample, 50 nanoseconds.

A reading method is as follows. A voltage is applied to the chalcogenideto measure a current passing through the chalcogenide, whereby aresistance value of the chalcogenide is read, and information isidentified. When the chalcogenide is in the set state at this time, evenif the temperature is raised up to the crystallization temperature, theset state is maintained because the chalcogenide is alreadycrystallized. However, when the chalcogenide is in the reset state, theinformation is destroyed. Therefore, for causing no the crystallization,a reading voltage must be set to a feeble voltage of, for example,approximately 0.3 V. The phase change memory is characterized in that:the resistance value in the phase change portion also changes from twodigits to three digits according to the crystal state or amorphousstate; and since a magnitude of the resistance value is read so as tocorrespond to binary information of “0” and “1”, as the differencebetween the resistance values is larger, the sense operation isperformed easier, and the read is performed at high speed. Hereinafter,the reading operation is called “read operation”.

As shown in FIG. 2, while a conventionally-known phase change memorycell 200 is mostly configured with a storage device 207 and a selectingtransistor 208, a configuration of a cross-point type memory cellincluding no selecting transistor is also considered. The storage device207 generally includes a chalcogenide 201, an upper electrode 203, and aplug electrode 202, the electrodes sandwiching the chalcogenide 201therebetween. Normally, although the plug electrode 202 mostly takes aplug structure having a smaller contact area with the chalcogenide thanthat of the upper electrode 203, a thin film may be used as theelectrode as described in Non-Patent Document 1. Note that “204”indicates a word line (WL), “205” indicates a source line, and “206”indicates a bit line (BL).

A general operation of the phase change memory is described inNon-Patent Document 2. The reset operation is performed by starting upthe word line and applying a current pulse having a pulse width of 20 to50 nanoseconds to the bit line. The set operation is performed bystarting up the word line and applying a current pulse having a pulsewidth of 60 to 200 nanoseconds to the bit line. The read operation isperformed by starting up the word line and applying a current pulsehaving a pulse width of 20 to 100 nanoseconds to the bit line. Thecurrent pulses used for the reset operation, the set operation, and theread operation flow from the bit line toward the source line in all ofthe operations or from the source line toward the bit line in all of theoperations.

Compared to the set operation required for raising the temperature onlyup to the crystallization temperature, a larger current is required forthe reset operation required for heating up to the melting point whichis higher than the crystallization temperature. By reducing the currentfor the reset operation, an area size of a selected device is reduced sothat high memory integration is made possible.

-   Patent Document 1: Japanese Patent Application Laid-Open Publication    No. 2004-272975-   Non-Patent Document 1: Y. H Ha and other 6 people, “An Edge Contact    Type Cell for Phase Change RAM Featuring Very Low Power    Consumption”, 2003 Symposium on VLSI Technology Digest Technical    Papers, USA, 2003, p. 175-176-   Non-Patent Document 2: H. Horii and other 7 people, “A Novel Cell    Technology Using N-doped GeSbTe Films for Phase Change RAM”, 2003    Symposium on VLSI Technology Digest Technical Papers, USA, 2003, p.    177-178

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention

As described in the “BACKGROUND ART”, while the phase change memory isrewritable with high speed and low power consumption compared to theFLASH memory which is a currently-common semiconductor nonvolatilememory, considering high integration is inferior compared to the FLASHmemory. For example, when a memory array is configured with aconventional-type phase change memory cell shown in FIG. 2, if it isassumed that a minimum feature size is “F”, an area size per cell is 8F²also in an ideal designed case. Compared to this, the area size per cellis 4F² in a most-advanced NAND-type FLASH memory, and an occupied areasize per bit is further reduced down to 2F² by using a multi level celltechnology.

Mainly, high integration has been rapidly advanced in the semiconductornonvolatile memory utilized for the mobile information terminalequipment and the like, and further, needs of low power consumption ofthe semiconductor nonvolatile memory are also high. It is predicted thatthere is a limitation of achieving the FLASH memory with low powerconsumption, and therefore, it is necessary to develop a highintegration technique of the phase change memory which is currentlydisadvantageous to high integration in order to realize thesemiconductor nonvolatile memory with low power consumption and highintegration.

Accordingly, an object of the present invention is to provide atechnique which can realize high integration in a semiconductor storagedevice such as a phase change memory.

The above and other objects and novel characteristics of the presentinvention will be apparent from the description of the specification andthe accompanying drawings.

Means for Solving the Problems

Outlines of typical ones of the inventions disclosed in the presentapplication will be briefly described as follows.

That is, a semiconductor storage device according to the presentinvention is characterized by including: a phase change thin film havingtwo stable phases of a crystal state with a low electric resistance andan amorphous state with a high electric resistance; first and secondelectrodes provided on one side of the phase change thin film; a thirdelectrode provided on the other side of the phase change thin film; afirst transistor whose drain terminal is connected to the firstelectrode, whose source terminal is connected to the third electrode,and whose gate terminal is connected to a first word line; and a secondtransistor whose drain terminal is connected to the second electrode,whose source terminal is connected to the third electrode, and whosegate terminal is connected to a second word line, wherein a first memorycell is provided with the first transistor and a first phase changeregion in the phase change thin film sandwiched between the firstelectrode and the third electrode, a second memory cell is provided withthe second transistor and a second phase change region in the phasechange thin film sandwiched between the second electrode and the thirdelectrode, the first transistor is turned off to carry a current fromthe first electrode to the third electrode in writing to the firstmemory cell, and the second transistor is turned off to carry a currentfrom the second electrode to the third electrode in writing to thesecond memory cell.

Also, the semiconductor storage device according to the presentinvention is characterized by including: a plurality of word lines; aplurality of bit lines intersecting the plurality of word lines; aplurality of memory cells arranged at the intersection of the pluralityof word lines and the plurality of bit lines, and each of memory cellsincluding a transistor and a storage device whose resistance changesaccording to storage information; a plurality of hierarchy switchesarranged in a space between one of the plurality of word lines andanother one at constant interval; a common data line; a switch circuitarranged in a space between the plurality of bit lines and the commondata line and for selecting one of the plurality of bit lines to connectthe one to the common data line; and a rewriting circuit connected tothe common data line, wherein a first hierarchy switch of the pluralityof hierarchy switches is inserted between a first bit line of theplurality of bit lines and a first memory cell of the plurality ofmemory cells and between a ground voltage terminal and the first memorycell, and a second hierarchy switch of the plurality of the hierarchyswitches is inserted between the first bit line and a second memory cellof the plurality of memory cells and between the ground voltage terminaland the second memory cell.

Further, the semiconductor storage device according to the presentinvention is characterized by having: first and second phase change thinfilms each having two stable phases of a crystal state with a lowelectric resistance and an amorphous state with a high electricresistance; a first electrode provided on one side of the first phasechange thin film; a second electrode provided on the other side of thefirst phase change thin film; a first transistor whose drain terminal isconnected to the first electrode, whose source terminal is connected tothe second electrode, and whose gate terminal is connected to a firstword line; a third electrode provided on one side of the second phasechange thin film; a fourth electrode provided on the other side of thesecond phase change thin film; and a second transistor whose drainterminal is connected to the third electrode, whose source terminal isconnected to the fourth electrode, and whose gate terminal is connectedto a second word line, and wherein, a first memory cell is provided withthe first transistor and a first phase change region in the phase changethin film sandwiched between the first electrode and the secondelectrode, a second memory cell is provided with the second transistorand a second phase change region in the phase change thin filmsandwiched between the third electrode and the fourth electrode, thefirst transistor is turned off and the second transistor is turned on tocarry a current from the first electrode to the fourth electrode in aninformation writing operation to the first memory cell, and the firsttransistor is turned on and the second transistor is turned off to carrya current from the first electrode to the fourth electrode in aninformation writing operation to the second memory cell.

EFFECTS OF THE INVENTION

Effects of typical ones of the inventions disclosed in the presentapplication will be briefly described as follows.

(1) A high-speed readable and high-capacity non-volatile semiconductorstorage device can be realized by using a semiconductor integratedcircuit device utilizing a technique of the present invention.

(2) Also, a high-reliability and high-performance micro-processor forembedded applications can be provided by mixedly mounting the device onthe same substrate that a semiconductor logic computing device isprovided on.

(3) Further, the device can be provided as a single chip.

BRIEF DESCRIPTIONS OF THE DRAWINGS

FIGS. 1A to 1E are diagrams showing structures, a circuit frame diagram,and operation methods of a storage device in a semiconductor storagedevice according to a first embodiment of the present invention;

FIGS. 2A and 2B are diagrams showing a structure and a circuit of aconventional method, respectively;

FIGS. 3A to 3D are diagrams each showing a plane structure of a mainportion of the storage device in the first embodiment of the presentinvention;

FIG. 4 is a sectional view of a principal part of the storage deviceaccording to the first embodiment of the present invention;

FIG. 5 is another sectional view of a principal part of the storagedevice according to the first embodiment of the present invention;

FIG. 6 is still another sectional view of a principal part of thestorage device according to the first embodiment of the presentinvention;

FIG. 7 is still another sectional view of a principal part of thestorage device according to the first embodiment of the presentinvention;

FIG. 8 is still another sectional view of a principal part of thestorage device according to the first embodiment of the presentinvention;

FIG. 9 is still another sectional view of a principal part of thestorage device according to the first embodiment of the presentinvention;

FIG. 10 is a layout diagram of a principal part of the storage deviceaccording to a second embodiment of the present invention;

FIG. 11 is a sectional view of a principal part of the storage deviceaccording to the second embodiment of the present invention;

FIG. 12 is another sectional view of a principal part of the storagedevice according to the second embodiment of the present invention;

FIG. 13 is still another sectional view of a principal part of thestorage device according to the second embodiment of the presentinvention;

FIG. 14 is still another sectional view of a principal part of thestorage device according to the second embodiment of the presentinvention;

FIG. 15 is still another sectional view of a principal part of thestorage device according to the second embodiment of the presentinvention;

FIG. 16 is still another sectional view of a principal part of thestorage device according to the second embodiment of the presentinvention;

FIG. 17 is a diagram showing a configuration example of a phase changememory array in a semiconductor information storage device according toa third embodiment of the present invention;

FIG. 18 is another diagram showing the configuration example of thephase change memory array in the semiconductor information storagedevice according to the third embodiment of the present invention;

FIGS. 19A and 19B are another diagrams each showing the configurationexample of the phase change memory array in the semiconductorinformation storage device according to the third embodiment of thepresent invention;

FIG. 20 is a diagram showing one example of a timing diagram in awriting operation of the phase change memory array of FIG. 17;

FIG. 21 is a diagram showing one example of a timing diagram in areading operation of the phase change memory array of FIG. 17;

FIG. 22 is a diagram showing a configuration example of a phase changememory array in a semiconductor information storage device according toa fourth embodiment of the present invention;

FIG. 23 is another diagram showing the configuration example of thephase change memory array in the semiconductor information storagedevice according to the fourth embodiment of the present invention;

FIGS. 24A and 24B are another diagrams each showing the configurationexample of the phase change memory array in the semiconductorinformation storage device according to the fourth embodiment of thepresent invention;

FIG. 25 is a diagram showing one example of a timing diagram in awriting operation of the phase change memory array of FIG. 18;

FIG. 26 is a diagram showing one example of a timing diagram in areading operation of the phase change memory array of FIG. 18;

FIG. 27 is a diagram showing a configuration example of a phase changememory array in a semiconductor information storage device according toa fifth embodiment of the present invention;

FIG. 28 is another diagram showing the configuration example of thephase change memory array in the semiconductor information storagedevice according to the fifth embodiment of the present invention;

FIGS. 29A to 29C are another diagrams each showing the configurationexample of the phase change memory array in the semiconductorinformation storage device according to the fifth embodiment of thepresent invention;

FIG. 30 is a diagram showing one example of a timing diagram in awriting operation of the phase change memory array of FIG. 27;

FIG. 31 is another diagram showing one example of the timing diagram inthe writing operation of the phase change memory array of FIG. 27; and

FIG. 32 is still another diagram showing one example of the timingdiagram in the writing operation of the phase change memory array ofFIG. 27.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described indetail with reference to the accompanying drawings. Note that componentshaving the same function are denoted by the same reference symbolsthroughout the drawings for describing the embodiment, and therepetitive description thereof will be omitted.

First Embodiment

Each of FIGS. 1A, 1B, and 1C shows a structure of a storage device arrayused in a semiconductor storage device of the present invention. A phasechange thin film (chalcogenide) 101 is sandwiched between an upper plugelectrode 102 and a lower electrode 104. A composition of the phasechange thin film 101 is Ge₂Sb₂Te₅, and compositions of the upper plugelectrode 102 and the lower electrode 104 are tungsten. A plug size 131is a diameter of 160 nm. The plug size varies according to a generationof a semiconductor process to be used. Although tungsten is frequentlyused as the composition of the upper plug electrode 102, any materialcan be used as long as having conductivity.

Each of FIGS. 1D and 1E shows a procedure when a writing and a readingis performed to a memory cell configuring the circuit shown in FIG. 1C.First, all word line voltages are set to 1.5 V to set all selectingtransistors to be ON state. Next, a pulse of 0 V is applied to a wordline 105 (WL1) of a selecting transistor 114 of a cell to which thewriting/reading is performed according to a writing and reading time toset the selecting transistor 114 to be OFF state. Thereafter, a currentpulse according to the reset operation, the set operation, and the readoperation is applied to terminals A and B to perform the writing andreading. Since the selecting transistor 114 becomes OFF state during 0 Vis applied thereto, almost all of the voltage applied to the terminals Aand B is applied to both ends of a phase change region (phase changestorage unit) 111 of a selected cell. In this manner, the writing andreading can be performed to a desired memory cell.

As already described with reference to FIG. 1E, a writing operation to aphase change region (phase change storage unit) 112 adjacent to thephase change region 111 can be performed by applying a voltage betweenthe terminals A and B, the voltage having opposite polarity to that ofthe writing to the phase change region 111 as shown in FIG. 1C.

As described above, it is found that the phase change region 111 and theselecting transistor 114 or the phase change region (phase changestorage unit) 112 and a selecting transistor 115 configure one memorycell.

When such a large current of 200 μA or larger is flown in the phasechange storage unit for a short time of approximately 50 ns, atransition from a crystallization state to an amorphous state can beperformed to be rewritten. This operation is called “reset operation”,and a current condition thereof changes depending on a composition ofthe phase change material, a structure and a size of the device, and thelike. Similarly, it is necessary to optimize a current conditionrequired for the set operation for each device to be manufactured.Although it is desirable that the selecting transistor configuring thememory cell is ideally a switch whose ON resistance is zero and whoseOFF resistance is infinite, both of ON/OFF state actually have finiteresistance values. Therefore, when an optimal current pulse as shown inFIG. 1D is applied to the phase change region 111, current is flown alsoin all of transistors and all of phase change storage units configuringthe circuit shown in FIG. 1C. Here, an ON resistance of the transistoris represented by “R_(ON)”, an OFF resistance thereof is represented by“R_(OFF)”, a set resistance of the phase change storage unit isrepresented by “R_(set)”, a reset resistance thereof is represented by“R_(reset)”, the number of memory cells configuring the circuit shown inFIG. 1C and connected in series is represented by “N”, and a value ofcurrent flowing between the terminals A and B is represented by“I_(AB)”. When the phase change storage unit of the selected memory cellis in the set state and a reset current “I_(reset)” is flown in thephase change storage unit, a current value “I₁” flowing in a phasechange storage unit belonging to a same array and in which an unselectedcell is in the set state is expressed as follows.I₁=I_(reset)×(R_(ON)/R_(OFF))×((R_(OFF)+R_(set))/(R_(ON)+R_(set)))  (1)

The I₁ indicates a value of a largest current flowing in the phasechange storage unit of the unselected cell being in a low resistancestate. Similarly, a value “I₂” of a largest current flowing in the phasechange storage unit of the unselected cell being in a high resistancestate (reset state) is expressed by the following equation.I₂=I_(reset)×(R_(ON)/R_(OFF))×((R_(OFF)+R_(set))/(R_(ON)+R_(reset)))  (2)

When both I₁ and I₂ become a negligible large value compared to thecurrent I_(set) used for the set operation, information disturbance ofthe unselected cell occurs such that resistance reduction of the highresistance state (transition from the reset state to the set state) dueto repetitive current pulse application or fixation of the lowresistance state due to the writing to the low resistance state (setstate). Accordingly, the selecting transistor must be designed so as tosatisfy at least the following equations.I₁<I_(set)  (3)I₂<I_(set)  (4)Ideally,I₁<10×I_(set)  (5)I₂<10×I_(set)  (6)

The following relationship is built between a voltage V_(AB) which isapplied between the terminals A and B and a value I_(read) of currentflowing in the phase change storage unit of the selected cell being inthe high resistance state (reset state) in the read operation.V_(AB)/I_(read)=R_(reset)+(N−1)×(R_(ON)²/R_(OFF))×((R_(OFF)+R_(set))/(R_(ON)+R_(set)))  (7)

The second term of the right side of Equation (7) is a parasiticresistance due to the unselected cell. The transistor must be designedso as to satisfy such that the parasitic resistance is sufficientlysmaller than the reset resistance, that is,(N−1)×(R_(ON)²/R_(OFF))×((R_(OFF)+R_(set))/(R_(ON)+R_(set)))<<R_(reset)  (8)and ideally,(N−1)×(R_(ON)²/R_(OFF))×((R_(OFF)+R_(set))/(R_(ON)+R_(set)))<10×R_(reset)  (9)and otherwise it becomes difficult to read information stored in thephase change storage unit. That is, a performance of the cell-selectingtransistor must be determined according to a characteristic of the phasechange storage unit so as to satisfy Equation (9). However, in the abovediscussion using Equations (1) to (9), all current values are handled aspositive values for simplification. Here, since only magnitude of theresistance value of the phase change storage unit and the MOS transistorconfiguring the memory cell array are handled, positive and negative ofthe current value does not affect a result of the discussion at all.

Next, a plane structure of a main portion of the memory cell will bedescribed.

FIGS. 3A to 3D show plane layouts of the phase change memory arrayhaving a cross sectional structure shown in FIG. 1A as following amanufacturing process of the device. First, FIG. 3A shows an activeregion (device active region) 301, a word line 302 of the MOStransistor, and a plug 303 connected to a diffusion layer to be a sourceregion and a drain region of the MOS transistor. This state correspondsto a state in which processes up to manufacturing a plug 106 iscompleted in the cross sectional view of FIG. 1A.

FIG. 3B shows a region 304 obtained by processing a stacked film of alower electrode and a phase change film formed on the plug 303. Thisstate corresponds to a state in which the process of the stacked film iscompleted by forming the lower electrode 104 and the phase change thinfilm 101 on the plug 106 in FIG. 1A.

FIG. 3C shows a plug 305 or a plug 306 formed on the phase change filmwhose process is completed in FIG. 3B, and further, a plug 307 connectedto the diffusion layer of the MOS transistor. The plugs 305 and 306 areconnected to the same phase change region in which the process iscompleted in FIG. 3B. A structure shown in FIG. 3C corresponds to astate in which all structures except for a word line (wiring layer) 108is completed in FIG. 1A.

FIG. 3D shows a completed state of the main portion of the memory cellin which the wiring layer to be connected to the plugs 305, 306, and 307is formed so that the process is finally completed. That is, “308”indicates a wiring portion connecting between the plug 307 connected tothe diffusion layer and the plugs 305 and 306 connected to the phasechange film, and the wiring portion corresponds to 108 in FIG. 1A.

According to the above manner, the main portion of the phase changememory cell array having the cross sectional structure shown in FIG. 1Aand having the equivalent circuit shown in FIG. 1C is completed.Although one memory cell region 309 is shown in FIG. 3D, it is foundthat a cell area size of approximately half of the conventional-typephase change memory cell can be realized even in a configuration havingone transistor+one phase change device by adopting a NAND-typestructure.

Next, a manufacturing method of the memory cell will be described.

First, a structure shown in the cross sectional view of the principalpart in FIG. 4 is manufactured by using normal semiconductor processes.A gate electrode 403 contacts with a gate dielectric film 401, asidewall 402, and a metal silicide 404. An adhesion layer 405 is formedin order to increase adhesion between a contact 406 and an inter-layerdielectric film 408 to prevent its peeling off.

Next, as shown in the cross sectional view of the principal part in FIG.5, a contact hole is formed and an adhesion layer 502 and a plug 501 areformed in the contact hole by chemical vapor deposition (CVD) method.TiN is used as a composition of the adhesion layer 502, and W is used asa composition of the plug material.

Further, as shown in the cross sectional view of the principal part inFIG. 6, a lower electrode 601 and a chalcogenide 602 are deposited bysputtering or vacuum vapor deposition, and then, an inter-layerdielectric film 603 is formed. For a composition of the chalcogenide, analloy of Ge—Sb—Te which is widely proven in a recording-type opticaldisk or a material obtained by adding additives in the alloy issuitable.

Next, as shown in the cross sectional view of the principal part in FIG.7, a contact hole is formed, and an adhesion layer 702 and an upperelectrode plug 701 contacted to the phase change film are formed in thecontact hole by chemical vapor deposition (CVD) method. W can be used asa material of the upper electrode plug.

Further, as shown in the cross sectional view of the principal part inFIG. 7, a contact hole is formed, and an adhesion layer 704 and acontact plug 703 for connecting between the upper electrode plug 701contacted to the phase change film and the diffusion layer of thetransistor are formed in the contact hole by chemical vapor deposition(CVD) method.

Still further, as shown in the cross sectional view of the principalpart in FIG. 8, an adhesion layer 802 and a connecting layer 801 forconnecting between the upper electrode plug and the diffusion layer ofthe transistor are formed.

Still further, as shown in the cross sectional view of the principalpart in FIG. 9, after forming a contact 901 contacted to the bit lineand an adhesion layer 902 thereof, a connecting layer 903 is formed, andthen, a bit line 904 is deposited by sputtering. Sequentially, aninter-layer dielectric film 905 is formed, and further, an upper wire isformed, thereby capable of manufacturing a desired memory.

In the present first embodiment, it is possible to manufacture thememory as following a normal CMOS logic mixedly mounting design rule,and the present first embodiment is suitable for a manufacture of alogic mixedly mounted memory.

As is apparent in FIG. 1, a source electrode of the transistor connectedto the storage media also serves as a drain electrode of an adjacentmemory cell by using a manner of the first embodiment, and the manner isadvantageous for high integration compared to a conventional structureshown in FIG. 2 in which one memory cell occupies one transistor. A sizeof a memory cell most highly integrated in the conventional structureshown in FIG. 2 is 8F² if it is assumed that a minimum feature size is“F”. Compared to this, since one transistor can be shared with theadjacent memory cells to each other in the first embodiment, an areasize of the memory cell in the case of the most highly integration canbe theoretically reduced down to 4F². That is, a memory cell suitablefor the high integration can be realized by using the structureaccording to the first embodiment.

A summary of the semiconductor storage device according to the firstembodiment is as follows.

In a memory cell formed of the phase change region (storage device) 111and the selecting transistor 114 shown in FIG. 1C, the phase changeregion 111 is formed of a device having a structure in which the phasechange thin film 101 is sandwiched between the upper plug electrode(first electrode) 102 and the lower electrode (third electrode) 104 asshown in FIG. 1B. Also, the phase change region 111 is formed of adevice having a pair-combined structure with the adjacent phase changeregion 112 which shares the lower electrode 104, and the device has asymmetrical structure putting the plug 106 on a center of the structureas shown by “113” in FIG. 1B. The phase change region 111 is formed justbelow the upper plug electrode 102 by carrying the writing current tothe phase change thin film 101 through the upper plug electrode 102 andthe lower electrode 104. Also, in the structure of this typical example,the upper plug electrode 102 shares the lower electrode 104 and thephase change thin film 101 with its adjacent cell including the upperplug electrode 103 as a second electrode. Similarly to the phase changeregion 111, the phase change region 112 of the adjacent cell is formedjust below the upper plug electrode 103 of the adjacent cell.

The selecting transistor 114 shown in FIG. 1C is configured withdiffusion layers 109 and 110, plugs 107 and 106 respectively connectedto the diffusion layers 109 and 110, and a word line (gate electrode)105 shown in FIG. 1A, and such a structure is provided that each of thediffusion layer and the plug are shared with another selectingtransistor configuring its adjacent cell.

An operation of the memory cell including the selecting transistor 114connected to the word line 105 (WL1) shown in FIGS. 1A and 1C is asfollows. First, FIG. 1D shows a timing chart of a voltage pulse appliedto the word line 105 (WL1). Also, current (C→D) indicates a value ofcurrent flowing in a direction from C to D between C and D in FIG. 1C.

First, all word lines including the word line 105 (WL1) are maintainedat 1.5 V which is in ON state of the selecting transistor so that thereis provided a state of not applying voltage to both ends of all of thephase change storage units. Next, for writing data in the phase changeregion 111, a voltage pulse shown in FIG. 1D is applied to the word line105 (WL1) connected to the gate electrode of the selecting transistor114 configuring the memory cell together with 111. When the gate voltageof the selecting transistor 114 returns back to 0 V, the selectingtransistor 114 is turned to OFF state, so that the current (C→D) isflown between both ends of C and D of the phase change region (phasechange storage unit) 111 connected to the selecting transistor 114 inparallel, thereby performing the writing operation of set and reset. Asa result of the above-described operation, current is flown from theupper plug electrode 102 to the lower electrode 104 shown in FIG. 1A atthe set operation and the reset operation. Thereby, the phase changeregion 111 is formed inside of the phase change thin film 101 locatedjust below the upper plug electrode 102, and the phase change region 111becomes the low resistance state which is crystallized after the setoperation and the phase change region 111 becomes the high resistancestate which is amorphized after the reset operation, so that informationof “1” and “0” are written therein. The resistance values are read bythe read operation shown in FIG. 1D.

FIG. 1E shows a procedure of a pulse application in a case of performingthe writing operation to a cell adjacent to the phase change region(phase change storage unit) 111, that is a memory cell formed of thephase change region 112 and the selecting transistor 115. Similarly tothe writing to 111, first, all of the word lines are maintained at 1.5V, so that there is realized a state of no applying voltage to both endsof all of the phase change storage units. And then, a voltage pulseshown by voltage (WL2) in FIG. 1E is applied to a word line 108 (WL2).And then, current is made to carry in the memory cell array by using theterminals A and B so as to match the current (D→E) flowing betweenterminals D and E which are both ends of the phase change region 112with the current pulse shown in FIG. 1E. As shown in FIG. 1E, currenthaving a reverse direction of the writing to the phase change region 111is flown between the terminals A and B.

By performing the writing operation to the phase change region (phasechange storage unit) 112 as described above, current in the phase changeregion 112 is flown from the upper plug electrode 103 to the lowerelectrode 104, so that the writing operation is performed under asimilar condition to that of the phase change region 111 on a structureof an actual cell.

There is a method of adjusting heights of the current pulses shown inFIGS. 1D and 1E, that is, magnitudes of the writing and readingcurrents, by the magnitude of the voltage applied to the terminals A andB at both ends of the memory cell array shown in FIG. 1C as constantlymaintaining the height of the current pulse applied to the word line ofthe selected cell.

While the currents flowing between the terminals A and B have reversedirections when adjacent cells are compared to each other at thewriting, the currents flowing between the terminals A and B may havesame directions at the reading.

Preferably, the ON resistance of the selecting transistor has a smallvalue which is negligible compared to the resistance value of the lowresistance state of the phase change storage unit.

Preferably, the material of the phase change device is chalcogenide.

Second Embodiment

Regarding a memory cell having a structure not required for switchingthe direction of the current carry when the adjacent cell is selected toperform the writing operation in spite of having a configuration of thesame equivalent circuit as that of the first embodiment, a descriptionthereof will be described below.

FIG. 10 shows a layout of a principal part of a memory cell according toa second embodiment. Such a structure is manufactured that a plug 1005contacted to a chalcogenide 1004 and a plug 1002 contacted to adiffusion layer of a transistor have a word line 1003 therebetween andare connected by a wiring layer 1006 inside an active region 1001 toform one memory cell. If it is assumed that a minimum feature size is“F”, a distance between adjacent word lines is 2F.

The above-described memory cell is connected in series to a memory cellincluding a wiring layer 1007 adjacent thereto manufactured inside thesame active region 1001 via the diffusion layer, so that a memory cellarray equal to the equivalent circuit shown in FIG. 1B is formed astracking a route indicated by line G-G′.

Cross sectional views of principal parts of portions shown by line F-F′in the layout diagram of the principal part shown in FIG. 10 are shownin FIGS. 11 to 15. After forming the plug 501 by using processes ofhaving the same structure as that of the cross section shown in FIG. 5in a vertical direction, a chalcogenide layer 1101 and an upperelectrode 1102 are formed by using sputtering or vacuum vapor depositionmethod. In the present embodiment, the plug 501 configures the lowerelectrode of the phase change storage unit differing from that of thefirst embodiment.

FIG. 12 shows a structure in which the phase change film and the upperelectrode are processed and a plug 1201 for contacting to a wiring layeris formed thereon, and FIG. 13 shows a structure in which a plug 1301for contacting to a diffusion layer without interposing the phase changefilm is formed. And then, a connecting layer 1401 and a wiring layer1402 are formed as shown in FIG. 14 and are processed as shown in FIG.15, and then, a protective film 1501 is formed, thereby completing astructure of a main portion of the memory cell. Note that processes formanufacturing the structures shown in FIGS. 11 to 15 are similartechniques to that used for manufacturing the structure of the firstembodiment, and those details are omitted.

FIG. 16 shows a cross sectional structure indicated by line H-H′ whichis a cross section in a direction of the word line 1003 in FIG. 10. Itcan be confirmed that there is provided an SGI (shallow grooveisolation) structure 1601 for device isolation isolating a diffusionlayer 1602 and the active region in the memory cell array from eachother on a substrate. As a main portion of the memory cell, “1603”indicates a phase change film, “1604” indicates a lower electrode plugconnected to the phase change film, “1605” indicates an upper electrode,and “1606” indicates a wiring layer for connecting a phase changestorage unit.

A difference of the structure of the memory cell of the secondembodiment from that of the first embodiment becomes apparent fromcomparison of FIGS. 9 to 15. In the structure of the first embodiment,as shown in FIG. 9, it is found that cells adjacent to each other arearranged so as to have a physically symmetrical structure as putting aboundary line between both cells to a center. This symmetrical structureis a reason for causing the requirement of applying the current pulsewith opposite polarity when the writing operation is performed to theadjacent cell as shown in FIG. 1C. Compared to this, since memory cellsadjacent to each other have exactly the same structure in the structureof the second embodiment as shown in FIG. 15, it is unnecessary tochange the polarity of the writing current for each adjacent cell.

By using the structure of the second embodiment as described above,simplification of the writing operation is possible even if a degree ofintegration of the memory cell thereof is inferior to that of thestructure shown in the first embodiment so that a circuit configurationfor driving the memory cell is simplified. Accordingly, the structure ofthe second embodiment is suitable for a device having a slightly smallermemory capacity than that of the first embodiment.

On the other hand, in the second embodiment, device isolation requiredfor each memory cell in the conventional phase change memory cell havingone cell configured with one transistor+one phase change device isunnecessary as is apparent from the layout diagram shown in FIG. 10.Normally, when a minimum feature size is denoted by F, an area size ofapproximately 2F² for each one memory cell is required in order tomanufacture an SGI (shallow groove isolation) structure for deviceisolation between memory cells, and therefore, an occupation area permemory cell becomes correspondingly large. Accordingly, when thestructure of the second embodiment is used, it is possible tomanufacture an inexpensive phase change memory with realizing the higherintegration than that of the memory having the conventional structure.

Further, as is apparent from a plan arrangement diagram shown in FIG.10, a gate width of the MOS transistor can be equal to or wider thantwice of that of the arrangement of the ordinary memory cell arrayaccording to the structure of the second embodiment. That is, in thefirst embodiment, the gate width of the MOS transistor becomes equal tothe width of the active region 301 of the memory cell as shown in FIGS.3A to 3D. The gate width becomes the same size even in the arrangementgenerally used for the memory cell array with the conventional structureshown in FIG. 2. Compared to this, the width of the active region 1001in FIG. 10 is equal to or wider than twice of the active region 301shown in FIG. 3 so that the gate width of the MOS transistor becomescorrespondingly large, thereby reducing the ON resistance. That is, byusing the structure of the second embodiment, constraints of the ONresistance required for the MOS transistor defined by Equation (9) canbe satisfied more easily than that of the other structures even in acase of manufacturing a fine memory cell so as to be highly integrated.

Also, in the memory cell with the conventional structure such as shownin FIG. 2, a current driving ability of the MOS transistor per memorycell becomes a problem when the memory cell is highly integrated. As aresult, the size of the MOS transistor cannot be made small, andtherefore, there is an indication about such a possibility thatmicrofabrication of the whole memory cell becomes difficult. Compared tothis, according to the structure of the second embodiment, as reducingthe occupation area per memory cell even if the same microfabricationtechnique and the same phase change device are used, the current drivingability of the MOS transistor can be contrarily increased two times thememory cell with the conventional structure or more. That is, it isfound that the use of the structure of the second embodiment becomes ahopeful mean for solving the problem of the current driving ability ofthe selected MOS transistor which becomes serious when themicrofabrication technique is advanced in the future.

Third Embodiment

FIG. 17 shows a schematic diagram of a configuration of a phase changememory according to a third embodiment. That is, the phase change memoryis configured with a memory array, a multiplexer MUX, a row decoderXDEC, a column decoder YDEC, a reading circuit RC, and a rewritingcircuit PRGM0. The memory array is configured with memory blocks MB00 toMBmn configured with a plurality of memory cells. In the same figure,memory blocks configured with eight memory cells MC0 to MC7 is shown asone example. Each of the memory cells is arranged at each intersectionof bit lines BL0 to BLn and word lines WL00 to WL07, . . . , WLm0 toWLm7 to be destinations of output signals from the row decoder XDEC0 andbetween the bit lines BL0 to BLn and source lines (here, SL12 and SL34).Each of the source lines is shared by memory blocks adjacent to eachother. The memory block further includes a hierarchy switch HS0 insertedbetween a bit line and a memory cell. The hierarchy switch HS0 isconfigured with an NMOS transistor QMH in which a gate electrode isconnected to one of memory block selecting signals MBS0 to MBSm whichare output signals of the row decoder XDEC0, and it is connected suchthat a current path between the drain and the source is included in acurrent path between the bit line and the memory cell.

The multiplexer MUX is configured with a column selecting switch arrayCSWA and a discharge circuit DCCKT. The column selecting switch arrayCSWA is configured with CMOS transmission gates CSW0 to CAWn insertedbetween the bit lines BL0 to BLn and a common data line CD,respectively. Column selecting line pairs (YS0T, YS0B) to (YSnT, YSnB)to be output signals of the column decoder YDEC are connected to gateelectrodes of the CMOS transmission gates CSW0 to CAWn, respectively. Byan activation of one of the column selecting line pairs (YS0T, YS0B) to(YSnT, YSnB), a CMOS transmission gate corresponding thereto isactivated so that one of the bit lines BL0 to BLn is connected to thecommon data line CD. The discharge circuit DCCKT comprises NMOStransistors MN0 to MNn inserted between the bit lines BL0 to BLn and aground voltage VSS terminal, respectively. Column selecting lines YS0Bto YSnB are connected to gate electrodes of the NMOS transistors MN0 toMNn, respectively. By maintaining the column selecting lines YS0B toYSnB at the power source voltage VDD in stand-by, the NMOS transistorsMN0 to MNn are turned on so that the bit lines BL0 to BLn are driven tothe ground voltage VSS. Each of the reading circuit RC and the rewritingcircuit PRGM0 are connected to the above-mentioned common data line CD.Also, a row address determining signal XFLG to be an output of the rowdecoder XDEC0 is connected to the rewriting circuit PRGM0.

FIG. 18 shows a specific example of a configuration of the memory celland the memory block shown in FIG. 17. Each of the memory cells MC0 toMC7 have a configuration in which a storage device RM and a selectingtransistor QM are connected in parallel. And, each of the memory cellsis connected in series to each other. Here, two terminals of the storagedevice RM are distinguished from each other by naming as an upperelectrode “TE” and a lower electrode “BE” in order to correspond to thestructures shown in FIGS. 1 and 15. In a connection of adjacent cells toeach other, one upper electrode TE of the storage device RM is connectedto the other upper electrode or one lower electrode BE thereof isconnected to the other lower electrode (a specific configuration will bedescribed later).

FIG. 19A shows a layout diagram of the memory block shown in FIG. 18.The layout is characterized that a via and a contact for connecting thebit line and the source line to the memory block are shared by memoryblocks adjacent to each other. “AA” indicates a pattern showing anactive region to be a current path of the NMOS transistor. “FG”indicates a pattern showing the gate electrode of the NMOS transistorand corresponds to a memory block selecting signal MBS1 and word linesWL10 to WL17 in the circuit diagram shown in FIG. 18. “FM” indicates apattern showing a first metal layer and corresponds to a source lineSL12. “SM” indicates a pattern showing a second metal layer andcorresponds to a bit line BL0. “FV” indicates a pattern showing a firstvia for connecting the first metal layer and the second metal layer.“CL” indicates a pattern showing the chalcogenide film and correspondsto the storage device RM. “TC” indicates a pattern showing an uppercontact formed on an upper portion of the chalcogenide film. Note that,in FIG. 19A, a pattern showing a contact formed on a lower portion ofthe chalcogenide film is omitted for simplification.

FIG. 19B further shows a cross sectional structure corresponding to thelayout diagram. “1900” indicates a p-type semiconductor substrate or ap-well, “1901” indicates the gate electrode of the NMOS transistor, and“1902” indicates an n-type diffusion layer to be the source electrodeand the drain electrode of the NMOS transistor. “1910” indicates thefirst metal layer and “1911” indicates the second metal layer. “1920”indicates the chalcogenide film. “1930” indicates the first via forconnecting the first metal layer and the second metal layer, and “1931”indicates the upper contact for connecting the first metal layer and thechalcogenide film. “1932” indicates the lower contact for connecting theupper contact or the chalcogenide film to the source or drain voltage ofthe NMOS transistor. The chalcogenide films (that is, the storagedevices RM) in memory cells adjacent to each other are connected via thefirst metal layer or the p-type diffusion layer of the NMOS transistor.Based on the characteristics, the connection of adjacent cells to eachother is provided such that one upper electrode TE of the storage deviceRM is connected to the other upper electrode or one lower electrode isconnected to the other lower electrode in the circuit diagram shown inFIG. 18.

In the layout and the cross sectional structure shown above, the via andthe contact for connecting the bit line and the source line to thememory block are shared by memory blocks adjacent to each other. Thedevice isolation region inside of the memory array can be removed bysuch a structure so that the area size of the memory array can besuppressed.

FIG. 20 shows the writing operation of the memory array shown in FIG.17. In the following, an explanation is made by using an assumption thata memory cell inside of a memory block MBS10 is selected. First, thecolumn selecting switch CSW0 corresponding to the column selecting linepairs (YS0T, YS0B) selected by the column decoder YDEC is turned on sothat the bit line BL0 and the common data line CD are connected to eachother. Next, a selecting operation of the row system is performedaccording to transition of the row address XADD. As shown in FIG. 20,when a word line WL11 corresponding to an odd number address isselected, the word line WL11 maintained at the power source voltage VDDis driven to the ground voltage VSS so that a selecting transistor QM ina memory cell MC1 is cut off, thereby forming a current path flowingthrough selecting transistors QM in unselected memory cells MC0 and MC2to MC7, and the storage device RM in the selected memory cell MC1.Sequentially, a memory block selecting signal MBS1 maintained at theground voltage VSS is driven to the power source voltage VDD so that theNMOS transistor QMH in the hierarchy switch HS0 is turned on to connectbetween the bit line and the memory block MB1, thereby flowing arewriting current in the storage device in the selected memory cell MC1.Here, the row address determining signal XFLG maintained at the groundvoltage VSS is driven to the power source voltage VDD according to theodd number address so that current is applied in a direction from therewriting circuit PRGM0 toward the source line SL12 via the bit lineBL0. The rewriting current is designed such that its current value andan application time thereof take values corresponding to storageinformation. For example, when the storage information is “0”, a largereset current IR is applied for a short time. On the other hand, whenthe storage information is “1”, a set current IS smaller than the resetcurrent IR is applied for a longer time than that of the reset current.Finally, the memory block selecting signal MBS1 maintained at the powersource voltage VDD is driven to the ground voltage VSS, and the wordline WL11 maintained at the ground voltage VSS is driven to the powersource voltage VDD, respectively, and the column selecting line pairs(YS0T, YS0B) are deactivated to set the transistor MN0 to be on so thatthe bit line BL0 is driven to the ground voltage VSS, thereby returningback to the stand-by state. By such a control, current can be applied tothe storage device RM in a cell (here, the memory cell MC1) selected bythe odd number row address in the direction from the upper electrode TEtoward the lower electrode BE.

FIG. 20 also shows a writing operation when the word line WL10corresponding to an even number address is selected. The word line WL10maintained at the power source voltage VDD is driven to the groundvoltage VSS so that the selecting transistor QM in the memory cell MC0is cut off, thereby forming a current path flowing through the storagedevice RM in the selected memory cell MC0 and the selecting transistorsQM in unselected memory cells MC1 to MC7. Here, the row addressdetermining signal XFLG is maintained at the ground voltage VSSaccording to the even number address so that current is applied in adirection from the source line SL12 toward the rewriting circuit PRGM0via the bit line BL0. By such a control, current can be applied to thestorage device RM in a cell (here, the memory cell MC0) selected by theeven number row address in the direction from the upper electrode TEtoward the lower electrode BE. Thereby, phase-changing regions can beprovided on the lower electrode BE (that is the lower contact) side inall the storage devices RM (that is the chalcogenide film) so thatvariations of resistance values can be suppressed.

FIG. 21 shows a timing diagram of a reading operation in the memoryarray shown in FIG. 17. Even in the following, explanation is made by anassumption that a memory cell in the memory block MB10 is selected aswell as the case of FIG. 20. First, the column selecting switch CSW0corresponding to the column selecting line pairs (YS0T, YS0B) selectedby the column decoder YDEC is turned on so that the common data line CDand the bit line BL0 are connected to each other, thereby performing apre-charge of the bit line BL0 to have a reading voltage VRD by thereading circuit RC. The reading voltage VRD is designed to be setbetween the power source voltage VDD and the ground voltage VSS so asnot to cause storage information crash. Further, the selectingtransistor on the word line selected by the row decoder XDEC is cut offso that a current path is formed through the storage device RM in theselected memory cell, thereby generating a reading signal to the bitline BL0 and the common data line CD. Since the resistance value in theselected memory cell varies according to storage information, voltageoutputted to the common data line CD varies according to the storageinformation. Here, when the storage information is “1”, the resistancevalue in the memory cell is low so that the bit line BL0 and the commondata line CD are discharged toward the ground voltage VSS to have alower voltage than a reference voltage VREF. On the other hand, when thestorage information is “0”, the resistance value in the memory cell ishigh so that the bit line BL0 and the common data line CD are maintainedat a pre-charged state, that is the reading voltage VDR. A difference ofvoltages is determined by the reading circuit RC so that storageinformation in the selected memory cell is read. Finally, the columnselecting line pairs (YS0T, YS0B) is deactivated to set the transistorMNO to be on so that the bit line BL0 is driven to the ground voltageVSS, thereby returning back to the stand-by state.

Finally, an effect according to the third embodiment is described below.In the third embodiment, the via and the contact for connecting the bitline and the source line to the memory block are shared by memory blocksadjacent to each other as shown in FIG. 19 so that the device isolationregion in the memory array can be removed, thereby capable ofsuppressing the area size of the memory array. Also, as shown in FIGS.17 and 20, the direction of the rewriting current flowing in the bitline is controlled to the direction according to the row address byusing the row address determining signal XFLG so that phase-changingregions can be provided on the lower electrode BE (that is the lowercontacts) side in all the storage devices RM, thereby capable ofsuppressing variations of the resistance values.

Fourth Embodiment

In a fourth embodiment, another configuration of the memory array and anoperation thereof will be explained. FIG. 22 is a schematic diagramshowing a configuration of a phase change memory according to the fourthembodiment. Large differences of FIG. 22 from those of FIG. 17 are thefollowing two points. The first one is a removal of a connection wirebetween a row decoder XDEC1 and a rewriting circuit PRGM1 to remove therow address determining circuit XFLG. The second one is that there isadded a function of generating two signals for controlling theconnection between the memory block and the bit line in each memoryblock to the row decoder XDEC1.

FIG. 23 shows a configuration of a memory block according to the fourthembodiment. In FIG. 23, a memory block MB10 is shown as one example. Adifference from the memory block shown in FIG. 18 is a point ofproviding two pairs of hierarchy switches CHS0 and CHS1. Each hierarchyswitch is configured with two pairs of NMOS transistors QMH and QMS. Thetransistor QMH is inserted between the bit line BL0 and the memory cellMC0 to the memory cell MC7 to control a connection of the bit line BL0and the memory cells MC0 to MC7 as well as the hierarchy switch shown inFIG. 18. The transistor QMS is inserted between the memory cells MC0 toMC7 and the ground voltage terminal VSS to control a connection betweenthe memory cells MC0 to MC7 and the ground voltage terminal VSS. Amemory block selecting signal MBS10 is connected to each gate electrodeof the transistor QMS in the hierarchy switch CHS0 and the transistorQMH in the hierarchy switch CHS1. A memory block selecting signal MBS11is connected to each gate electrode of the transistor QMS in thehierarchy switch CHS1 and the transistor QMH in the hierarchy switchCHS0.

FIG. 24 shows a layout diagram of the memory block shown in FIG. 23.There are two characteristics of the layout as follows. The first one isthat patterns corresponding to a power feeder of the ground voltage VSSare arranged at two portions in the memory block. The second one is thata contact and a via used for a connection between a bit line and amemory cell are shared by memory blocks adjacent to each other.

“AA” indicates a pattern showing an active region to be a current pathof an NMOS transistor. “FG” indicates a pattern showing a gate electrodeof the NMOS transistor and corresponds to the main block selectingsignals MBS10 and MBS11, and the word lines WL10 to WL17 in the circuitdiagram shown in FIG. 23. “FM” indicates a pattern showing a first metallayer and is used for the power feeder of the ground voltage VSS. “SM”indicates a pattern showing a second metal layer and is used for aconnection of the memory cell. “TM” indicates a pattern showing a thirdmetal layer and is used for the bit line BL0. “FV” indicates a patternshowing a first via for connecting between the first metal layer and thesecond metal layer. “SV” indicates a pattern showing a second via forconnecting between the second metal layer and the third metal layer.“CL” indicates a pattern showing the chalcogenide film and correspondsto the storage device RM. “TC” indicates a pattern showing an uppercontact formed on an upper portion of the chalcogenide film. Note that,in FIG. 24, a pattern showing a contact formed on a lower portion of thechalcogenide film is omitted for simplification.

FIG. 24 show, further, a cross sectional structure corresponding to thelayout diagram. “2400” indicates a p-type semiconductor substrate or ap-well, “2401” indicates a gate electrode of the NMOS transistor, “2402”indicates an n-type diffusion layer to be a source electrode and a drainelectrode of the NMOS transistor, and “2403” indicates a deviceisolation region. “2410” indicates the first metal layer, “2411”indicates the second metal layer, and “2412” indicates the third metallayer. “2420” indicates the chalcogenide film. “2430” indicates thefirst via for connecting between the first metal layer and the secondmetal layer, “2433” indicates the second via for connecting between thesecond metal layer and the third metal layer, and “2431” indicates theupper contact for connecting between the first metal layer and thechalcogenide film. “2432” indicates the lower contact for connectingbetween the upper contact or the chalcogenide film and the sourcevoltage or the drain voltage of the NMOS transistor. In adjacent memorycells, the chalcogenide films (that is the storage devices RM) areconnected through the first metal layer or a p-type diffusion layer ofthe NMOS transistor.

In the layout and cross sectional structure described above, the bitline, the ground voltage VSS power feeder, and the memory block areconnected by using the first and second metal layers so that the bitlines can be arranged with a minimum pitch, thereby capable ofsuppressing the area size of the memory array.

FIG. 25 shows a writing operation of the memory array shown in FIG. 22.FIG. 25 shows a timing diagram with an assumption that a memory cell inthe memory block MBS10 is selected. Differences shown in FIG. 25 fromthat shown in FIG. 20 are the following two points. The first one isthat, when a memory cell corresponding to an odd number row address suchas a word line WL11 is selected, the memory block selecting signal MBS11maintained at the ground voltage VSS is driven to the power sourcevoltage VDD so that the bit line BL0 and the memory cells MC0 to MC7 areconnected to form a current path. The second one is that, when a memorycell corresponding to an even number row address such as a word lineWL10 is selected, the memory block selecting signal MBS10 maintained atthe ground voltage VSS is driven to the power source voltage VDD so thatthe bit line BL0 and the memory cells MC0 to MC7 are connected to form acurrent path. FIG. 26 shows a reading operation of the memory arrayshown in FIG. 22. Also in this operation, a selecting operation similarto the rewriting operation shown in FIG. 25 is performed.

By the above-mentioned configuration and operation, it is made possibleto apply current to the storage device RM in each memory cell in thedirection from the upper electrode TE to the lower electrode BE in spiteof maintaining the same direction of the rewriting current flowing inthe bit line BL0. Thereby, phase-changing regions can be provided on thelower electrode BE (that is the lower contact) side in all the storagedevices RM, so that variations of resistance values can be suppressed.Also, the configuration and operation of the rewriting circuit PRGM1shown in FIG. 22 are simplified so that the area size of the circuitblock can be suppressed.

Finally, an effect according to the fourth embodiment is describedbelow. In the fourth embodiment, the connection of the bit line and thesource line to the memory block is controlled by using two pairs ofhierarchy switches CHS0 and CHS1 as shown in FIG. 23 so that it is madepossible to apply the rewriting current to the storage device RM in eachmemory cell in the direction from the upper electrode TE toward thelower electrode BE. Also, since the current can be driven only in onedirection in the rewriting circuit PRGM1, a circuit configurationthereof is simplified so that the area size of the circuit block can besuppressed.

Fifth Embodiment

In a fifth embodiment, still another configuration and operation of amemory array will be explained. FIG. 27 shows a configuration of thememory array and a memory block according to the fifth embodiment. Thememory array according to the fifth embodiment is characterized byforming a current path of a memory cell by using two bit lines in orderto block inflow of feeble current into an unselected memory cell in amemory block connected to a selected word line. Also, characteristics ofa circuit configuration of the fifth embodiment are the following fourpoints.

A first characteristic is to provide a configuration in which a memoryblock is connected to two bit lines adjacent to each other. That is,when explanation is made with taking a memory block MB1(2k) as anexample with reference to FIG. 28, each of memory cells MC0 to MC7 andeach of bit lines BL(2k) and BL(2k+1) are connected via hierarchyswitches HS10 and HS11 arranged at both ends of the memory block. Eachof the hierarchy switches HS10 and HS11 is configured with an NMOStransistor QMH and is controlled by a memory block selecting signalMBS10 to be an output signal from a row decoder XDEC2.

A second characteristic is to connect a memory block intersected witheach word line to a bit line pair in every one block. When a memoryblock MB1(2k) and a memory block MB1(2k+1) are focused, a memory blockcorresponding to an even number column address such as the memory blockMB1(2k) is connected to a bit line pair (BL(2k), BL(2k+1)) by using amemory block selecting signal MBS10. On the other hand, a memory blockcorresponding to an odd number column address such as the memory blockMB1(2k+1) is connected to a bit line pair (BL(2k+1), BL(2k+2)) by usinga memory block selecting signal MBS11.

A third characteristic is to arrange a reading circuit and a rewritingcircuit in each adjacent bit lien pair. In FIG. 27, regarding a bit linepair (BL(2k), BL(2k+1)), a reading circuit RCk and a rewriting circuitPRGM1 k are arranged via a multiplexer MUX1 and a common data line CD0 kdescribed later. Also, regarding bit line pair (BL(2k+2), BL(2k+3)), areading circuit RC(k+1) and a rewriting circuit PRGM1(k+1) are arrangedvia the multiplexer MUX1 and a common data line CD0(k+1). These readingcircuit group and rewriting circuit group are clearly shown as a readingand writing circuit array PSA0. On the other hand, regarding a bit linepair (BL(2k−1), BL(2k)), a reading circuit RC(k−1) and a rewritingcircuit PRGM1(k−1) are arranged via the multiplexer MUX1 and a commondata line CD1(k−1). Also, regarding a bit line pair (BL(2k+1),BL(2k+2)), the reading circuit RCk and the rewriting circuit PRGM1 k arearranged via the multiplexer MUX1 and the common data line CD1 k. Thesereading circuit group and writing circuit group are clearly shown as areading and writing circuit array PSA1.

A fourth characteristic is that the multiplexer MUX1 is configured withtwo column selecting switch arrays CSWA0 and CSWA1 and a dischargecircuit DCCKT, and is controlled by using a signal outputted from anarray control circuit ACTL according to a column address and a rowaddress. Each of the column selecting switch arrays CSWA0 and CSWA1 hasthe same configuration as the column selecting switch array CSWA shownin FIG. 17. However, a CMOS transmission gate is represented by a switchsymbol for simplification. One column selecting switch array CSWA0 is acircuit block for connecting between the bit line and the reading andwriting circuit array PSA0. A column switch arranged in a bit linecorresponding to an even number column address such as CSW(2k) andCSW(2k+2) is controlled by a global memory block selecting signalGMBS01. A column switch arranged in a bit line corresponding to an oddnumber column address such as CSW(2k+1) is controlled by a global memoryblock selecting signal GMBS00. Another column selecting switch arrayCSWA1 is a circuit block for connecting between the bit line and thereading and writing circuit array PSA1. A column switch arranged in abit line corresponding to an even number column address such as CSW(2k)and CSW(2k+2) is controlled by a global memory block selecting signalGMBS10. A column switch arranged in a bit line corresponding to an oddnumber column address such as CSW(2k+1) is controlled by a global memoryblock selecting signal GMBS11. Also, in the discharge circuit DCCKT, anNMOS transistor arranged in a bit line corresponding to an even numbercolumn address such as MN(2k) and MN(2k+2) is controlled by a dischargestarting signal DCE0. An NMOS transistor arranged in a bit linecorresponding to an odd number column address such as MN(2k+1) iscontrolled by a discharge starting signal DCE1.

FIG. 29 shows a layout diagram of the memory block shown in FIG. 28. Thelayout is characterized by a connection of memory cells by using thefirst metal layer, and at the same time, a connection between the memoryblock and the bit line by using the second metal layer.

“AA” indicates a pattern showing an active region to be a current pathof an NMOS transistor. “FG” indicates a pattern showing a gate electrodeof the NMOS transistor and corresponds to a memory block selectingsignal MBS10 and MBS11 and word lines WL10 to WL17. “FM” indicates apattern showing a first metal layer and “SM” indicates a pattern showinga second metal layer. “TM” indicates a pattern showing a third metallayer which is used for the bit lines BL(2k) and BL(2k+1). “FV”indicates a pattern showing a first via for connecting between the firstmetal layer and the second metal layer. “SV” indicates a pattern showinga second via for connecting the second metal layer and the third metallayer. “CL” indicates a pattern showing a chalcogenide film andcorresponds to the storage device RM. “TC” indicates a pattern showingan upper contact formed on an upper portion of the chalcogenide film.Note that, in FIG. 29, a pattern showing a contact formed on a lowerportion of the chalcogenide film is omitted for simplification.

FIG. 29 shows, further, a sectional view corresponding to the layoutdiagram. “2900” indicates a p-type semiconductor substrate or a p-well,“2901” indicates a gate electrode of the NMOS transistor, “2902”indicates an n-type diffusion layer to be source and drain electrodes ofthe NMOS transistor, and “2903” indicates a device isolation region.“2910” indicates the first metal layer, “2911” indicates the secondmetal layer, and “2912” indicates the third metal layer. “2920”indicates the chalcogenide film. “2930” indicates the first via forconnecting between the first metal layer and the second metal layer,“2933” indicates the second via for connecting between the second metallayer and the third metal layer, and “2931” indicates the upper contactfor connecting between the first metal layer and the chalcogenide film.“2932” indicates the lower contact for connecting between the uppercontact or the chalcogenide film and the source or drain voltages of theNMOS transistor. The chalcogenide films (that is, the storage devicesRM) in memory cells adjacent to each other are connected via the firstmetal layer or the p-type diffusion layer of the NMOS transistor.

In the above-described layout and the cross sectional structure, sincethe bit line and the memory block are connected by using the secondmetal layer, it is made possible to form the bit line and the sourceline in the same direction viewed from the memory cell by using the bitline pairs each arranged at a minimum pitch interval as arranging thebit lines each at a minimum pitch interval. Thereby, it is possible toblock inflow of feeble current to the unselected memory cell in thememory block connected to the selected word line so that devicecharacteristic degradation and storage information crash of theunselected memory cell can be avoided.

FIG. 30 shows a writing operation of the memory array shown in FIG. 27.FIG. 30 shows a timing diagram by an assumption that a memory cell in amemory block MBS1(2k) is selected. First, an operation of writingstorage information in the memory cell MC1 on the word line WL11 will beexplained. In this case, differences from the operation shown in FIG. 20are the following two points. Firstly, the one point is that, thedischarge start signal DCE1 maintained at the power source voltage VDDis driven to the ground voltage VSS to cut off a transistor MN(2k) inthe discharge circuit DCCKT, and at the same time, the global memoryblock selecting signal GMBS01 maintained at the ground voltage VSS isdriven to the power source voltage VDD, so that the column switch isactivated, thereby connecting between the bit line BL(2k) and therewriting circuit PRGM0 k in the reading and writing circuit array PSA0.Secondly, the another point is that, the memory block selecting signalMBS10 maintained at the ground voltage VSS is driven to the power sourcevoltage VDD, so that the hierarchy switch is activated, therebyconnecting between the bit line pairs (BL(2k), BL(2k+1)) and the memorycells MC0 to MC7. By such a selecting operation, there is provided acurrent path flowing from the rewriting circuit PRGM0 k in the readingand writing circuit array PSA0 to the terminal of the ground voltage VSSvia the bit line BL(2k), the memory block MB1(2k), the bit lineBL1(2k+1), and the transistor MN(2k+1) in the discharge circuit DCCKT.Thereby, the rewriting current can be applied to the storage device RMin the memory cell corresponding to the odd number row address such asMC1 in the direction from the upper electrode TE to the lower electrodeBE.

Next, a writing operation of storage information in the memory cell MC0on the word line WL10 will be explained. Also in this case, similarly tothe previous description, the discharge start signal DCE0 maintained atthe power source voltage VDD is driven to the ground voltage VSS, sothat the transistor MN(2k+1) in the discharge circuit DCCKT is cut off,and at the same time, the global memory block select signal GMBS00maintained at the ground voltage VSS is driven to the power sourcevoltage VDD, so that the column switch is activated, thereby connectingbetween the bit line (BL(2k+1)) and the rewriting circuit PRGM0 k in thereading and writing circuit array PSA0. Sequentially, the memory blockselecting signal MBS10 maintained at the ground voltage VSS is driven tothe power source voltage VDD, so that the hierarchy switch is activated,thereby connecting between the bit line pair (BL(2k), BL(2k+1)) and thememory cells MC0 to MC7. By such a selecting operation, there isprovided a current path flowing from the rewriting circuit PRGM0 k inthe reading and writing circuit array PSA0 to the terminal of the groundvoltage VSS via the bit line BL(2k+1), the memory block MB1(2k), the bitline BL1(2k), and the transistor MN(2k) in the discharge circuit DCCKTis formed. Thereby, the rewriting current can be applied to the storagedevice RM in the memory cell corresponding to the even number rowaddress such as MC0 in the direction from the upper electrode TE to thelower electrode BE.

Also, when the memory cell in the memory block corresponding to the oddnumber column address such as MBS1(2k+1) is selected, the rewritingcircuit PRGM0 k in the reading and writing circuit array PSA1, the bitline pairs (BL(2k+1), BL(2k+2)), and the memory block are connected byusing the global memory block selecting signals GMBS10 and GMBS11, andthe memory block selecting signal MBS11. The operation is shown in FIG.31.

FIG. 32 shows a reading operation of the memory array shown in FIG. 27.FIG. 32 shows a timing diagram when the reading is performed in an orderof the memory cells MC1 and MC0 as one example with an assumption thatthe memory cells in the memory block MBS1(2k) are selected. In theseoperations, the selecting operation of the memory cell is performed in amanner similar to the rewriting operation shown in FIG. 30.

Finally, effects obtained by the above-described configuration andoperation will be described. In the fifth embodiment as shown in FIG.27, the bit line pair and the memory block are connected by using twopairs of hierarchy switches HS0 and HS1, so that the rewriting currentcan be applied to the storage device RM in each memory cell in thedirection from the upper electrode TE to the lower electrode BEsimilarly to the third embodiment and the fourth embodiment. Therefore,a phase change region can be formed on the same position on the storagedevice, so that variation of resistance values can be suppressed. Also,since the bit line and the source line which are viewed from the memorycell are formed by the bit line pair, inflow of current into theunselected cell on the selected word line can be avoided. Therefore,degradation of the device characteristics of the unselected cell andstorage information crash can be avoided. By these effects, a phasechange memory with high integration and with high reliability can berealized.

In the foregoing, the invention made by the inventors of the presentinvention has been concretely described based on the drawings. However,it is needless to say that the present invention is not limited to theforegoing embodiments and various modifications and alterations can bemade within the scope of the present invention.

INDUSTRIAL APPLICABILITY

According to significant spread of mobile equipment, demand of anonvolatile memory has been increased. Particularly, there is demanded amemory in which embodiment with a logic circuit is easy, high-speedwriting is possible, the number of rewritable times is large, and drivevoltage is low. A phase change memory is a device expected as a memoryhaving all these features.

The present invention for realizing stable writing of a phase changememory largely contributes to practical use of a phase change memory.Particularly, in a mixedly mounted microprocessor with a nonvolatilememory and an IC card, a possibility of widely use of the presentinvention is significantly high.

The invention claimed is:
 1. A semiconductor storage device comprising:a phase change thin film having two stable phases of a crystal statehaving a first resistance value and an amorphous state having aresistance value higher than the first resistance value; first andsecond electrodes provided on one side of the phase change thin film; athird electrode provided on the other side of the phase change thinfilm; a first transistor whose drain terminal is connected to the firstelectrode, whose source terminal is connected to the third electrode,and whose gate terminal is connected to a first word line; and a secondtransistor whose drain terminal is connected to the second electrode,whose source terminal is connected to the third electrode, and whosegate terminal is connected to a second word line, wherein a first memorycell is configured with the first transistor and a first phase changeregion in the phase change thin film sandwiched between the firstelectrode and the third electrode, a second memory cell is configuredwith the second transistor and a second phase change region in the phasechange thin film sandwiched between the second electrode and the thirdelectrode, at a writing time to the first memory cell, the firsttransistor is turned off to carry a current from the first electrode tothe third electrode, and at a writing time to the second memory cell,the second transistor is turned off to carry a current from the secondelectrode to the third electrode.
 2. The semiconductor storage deviceaccording to claim 1, further comprising a current controllingtransistor connected to the first memory cell and the second memory cellin series.
 3. The semiconductor storage device according to claim 2,wherein a plurality of the first and second memory cells arerepetitively connected in series, and if it is assumed that the numberof memory cells connected in series in a memory cell array is N, an ONresistance R_(ON) and an OFF resistance R_(OFF) of a transistorconfiguring the memory cell, a resistance value R_(reset) when the phasechange thin film configuring the memory cell is in an amorphous state,and a resistance value R_(set) when the phase change thin film is in acrystal state satisfy a condition of(N−1)×(R_(ON)²/R_(OFF))×((R_(OFF)+R_(set))/(R_(ON)+R_(set)))<10×R_(reset).
 4. Thesemiconductor storage device according to claim 1, wherein at a readingtime, only the transistor of one selected from the memory cells isturned off, and the transistor of the unselected memory cell is turnedon, so that a reading voltage is applied to both the electrodes of oneselected from the phase change regions to read data of the selectedmemory cell, and at a writing time, only the transistor of one selectedfrom the memory cells is turned off, and the transistor of theunselected memory cell is turned on, so that a writing voltage isapplied to both the electrodes of one selected from the phase changeregions to apply a writing current to the selected phase change region.5. The semiconductor storage device according to claim 1, wherein whenthe writing to one selected from the memory cells is performed, thewritings to the adjacent memory cells in the memory cells connected inseries are performed by applying currents with mutually reversepolarities.
 6. The semiconductor storage device according to claim 1,wherein such an arrangement is formed that a plurality of memory cellarrays in which the same number of memory cells are connected in seriesare disposed, and that word lines in a direction perpendicular to thememory cell arrays, and the memory cells to be written and read areselected according to a combination of the memory cell arrays and theword lines.
 7. The semiconductor storage device according to claim 6,wherein when information is written in the first memory cell, the firsttransistor is turned to an off state via the first word line connectedto a gate electrode of the first transistor configuring the selectedfirst memory cell, and a first current pulse is applied to the memorycell array including the selected first memory cell and connected inseries so that the writing is performed, and when a writing is performedto the second memory cell adjacent to the first memory cell via thesecond word line adjacent to the first word line, a second current pulsehaving a reverse direction to that of the first current pulse is appliedto the cell array including the first and second memory cells.
 8. Thesemiconductor storage device according to claim 1, wherein when areading of one selected from the memory cells is performed, a pulsealways having a same condition to all the memory cells to be read isused for a reading voltage applied to both ends of one of the memorycells connected in series.
 9. A semiconductor storage device comprising:a plurality of word lines; a plurality of bit lines intersecting withthe plurality of word lines; a plurality of memory cells arranged at theintersections of the plurality of word lines and the plurality of bitlines and each including a transistor and a storage device whoseresistance changes according to storage information; a plurality ofhierarchy switches each arranged between the plurality of word lines ata constant interval; a common data line; a switch circuit arrangedbetween the plurality of bit lines and the common data line and forselecting one of the plurality of bit lines to connect the one to thecommon data line; and a rewriting circuit connected to the common dataline, wherein a first hierarchy switch of the plurality of hierarchyswitches is inserted between a first bit line of the plurality of bitlines and a first memory cell of the plurality of memory cells andbetween a ground voltage terminal and the first memory cell, and asecond hierarchy switch of the plurality of the hierarchy switches isinserted between the first bit line and a second memory cell of theplurality of memory cells and between the ground voltage terminal andthe second memory cell.
 10. The semiconductor storage device accordingto claim 9, wherein when the first bit line and the first memory cellare connected to each other by the first hierarchy switch, and when theground voltage terminal and the second memory cell are connected to eachother by the second hierarchy switch, a current flows in the first andsecond memory cells in a first direction, and when the ground voltageterminal and the first memory cell are connected to each other by thefirst hierarchy switch, and when the first bit line and the secondmemory cell are connected to each other by the second hierarchy switch,a current flows in the first and second memory cells in a seconddirection, and directions of the first current and the second currentare reverse to each other.
 11. The semiconductor storage deviceaccording to claim 10, wherein the storage device and the transistor areconnected in parallel in each of the plurality of memory cells.
 12. Thesemiconductor storage device according to claim 11, wherein the storagedevice is a material containing a chalcogenide material.
 13. Asemiconductor storage device comprising: a first phase change thin filmhaving two stable phases of a crystal state having a first resistancevalue and an amorphous state having a resistance value higher than thefirst resistance value; a first electrode provided on one side of thefirst phase change thin film; a second electrode provided on the otherside of the first phase change thin film; a first transistor whose drainterminal is connected to the first electrode, whose source terminal isconnected to the second electrode, and whose gate terminal is connectedto a first word line; a second phase change thin film having two stablephases of the crystal state having the first resistance value and theamorphous state having the resistance value higher than the firstresistance value; a third electrode connected to the second electrodeand provided on one side of the second phase change thin film; a fourthelectrode provided on the other side of the second phase change thinfilm; and a second transistor whose drain terminal is connected to thethird electrode, whose source terminal is connected to the fourthelectrode, and whose gate terminal is connected to a second word line,wherein a first memory cell is configured with the first transistor anda first phase change region in the phase change thin film sandwichedbetween the first electrode and the second electrode, a second memorycell is configured with the second transistor and a second phase changeregion in the phase change thin film sandwiched between the thirdelectrode and the fourth electrode, at a writing operation ofinformation to the first memory cell, the first transistor is turned offand the second transistor is turned on to carry a current from the firstelectrode to the fourth electrode, and at a writing operation ofinformation to the second memory cell, the first transistor is turned onand the second transistor is turned off to carry a current from thefirst electrode to the fourth electrode.